An electronic image sensor captures images using light-sensitive photodetectors that convert incident light into electrical signals. Image sensors are generally classified as either front-illuminated image sensors or back-illuminated image sensors. FIG. 1 is a simplified cross-section of a front-illuminated image sensor through three pixels 101, 102, 103. The illustrated image sensor 100 is a pmos image sensor, which includes pixels 101, 102, 103 formed within a p++ substrate 2 on p-epi silicon layer 3. Photodetectors 91, 92, 93 are formed within this sensor layer 4. An n-type pinning layer 27 is formed over each photodetector 91, 92, 93. One or more shallow trench isolation (STI) regions 5 are formed within each pixel 101, 102, 103. A different n-type pinning layer 26 lines the STI trench, the purpose of which is to reduce dark current generation due to dangle silicon bonds along the STI sidewalls.
A transfer gate 10 is used to transfer the collected photo-generated charges 31 from the photodetector 91 to a charge-to-voltage converter 28. The illustrated charge-to-voltage converter 28 is configured as a floating diffusion. The converter 28 converts the charge into a voltage signal. Transistors within the pixel array (see FIG. 2) amplify this voltage signal and relay the information to external circuitry where the image is further processed. Referring to FIG. 2, a source-follower transistor 173 buffers the voltage signal stored in the charge-to-voltage converter 28. A reset transistor 172 is used to reset the converter 28 to a known potential prior to pixel readout. The output voltage from the source-follower 174 drives a column line that is connected to external circuitry at the periphery of the imager.
Returning to FIG. 1 the charge-to-voltage converter 28 resides in a shallow n-well 29 that isolates the p+ converter 28 from the photodiode 91 and substrate 2. The shallow n-well 29 is biased to a known voltage level VDD through a well contact 37. VDD also biases the n-type pinning layer 27, the n-type pinning layer 26 that lines the STI trench, and the deep n-well 21. The deep n-well 21 is electrically connected to the shallow n-well 29 by the additional n-type implant 30. Biasing both the shallow n-well 29 and deep n-well 21 to a known potential with respect to ground steers the photo-generated charges 31 into the photodetector 91. Biasing both wells performs the additional function of dramatically reducing electrical crosstalk. For example, photo-generated charges 33 below the position where the electric field is zero, commonly referred to as the vertical overflow drain position (dashed line 8) are swept into the substrate. The vertical overflow drain nearly eliminates electrical crosstalk by preventing photo-generated charges from diffusing into adjacent pixels, and therefore improving MTF performance of the device.
The well contact 37 is positioned at the periphery of the image sensor. Other n-well contacts are periodically spaced throughout imaging area (not shown) to reduce the effective resistance of the wells 21, 29 and to reduce or eliminate well bounce.
For the front-illuminated image sensor of FIG. 1, conductive interconnects 51, 52, 53, such as gates and connectors, are formed in a circuit layer 50. Unfortunately, the positioning of conductive interconnects 51, 52, 53, and various other features associated with the circuit layer 50, over the photodetectors 91, 92, 93 adversely impacts the fill factor and quantum efficiency of the image sensor 100. This is because light 19 from a subject scene must pass through circuit layer 50 before striking the front silicon surface 9 and is detected by photodetectors 91, 92, 93.
FIG. 3 illustrates a cross-sectional view of a portion of the standard CMOS circuitry that resides at the periphery of the image sensor. The standard PMOS 142 and NMOS 143 transistors, and their associated shallow n-well 140 and p-well 141 implants are unaffected by the deep well implant 21 (FIG. 1) in the imaging area (pixels 101, 102, 103 of FIG. 1). The p-type 142 and n-type 143 transistors in the CMOS circuitry outside of imaging area are fabricated using the standard CMOS process flow. During fabrication of the color filter array, the CMOS circuitry is protected from back illumination by an opaque lightshield (not shown). The lightshield can be metal, a stacked layer of red, green, and blue color filter array material, or a unique light absorbing material.
FIG. 4 illustrates a cross-section of a back-illuminated image sensor. Back illumination addresses the fill factor and quantum efficiency issues by constructing the image sensor such that the light from a subject scene is incident on a backside of a sensor layer. The “frontside” 9 of sensor layer 213 is conventionally known as the side of sensor layer 213 that abuts the circuit layer 50, while the “backside” 250 is the side of the sensor layer 213 that opposes the frontside 9. Typically, the circuit layer 50 is attached to a support substrate (not shown). This backside configuration allows light 219 to strike the backside 250 of the sensor layer 213, where it is detected by the photodetectors 91, 92, 93. The detection of light 219 by photodetectors 91, 92, 93 is no longer impacted by the metallization level 51, 52, 53, interconnects 37, and other features of the circuit layer such as the gates 10.
In an effort to increase the number of pixels provided in an image sensor, pixel size has been decreasing. An advantage of moving to smaller pixels is that it increases the resolution of the image for a fixed optical format. Specifically, smaller pixels have a better modulation transfer function (MTF), and can thus discriminate fine details in an image, such as the lines on a finely striped shirt. However, as illustrated in FIG. 4, reducing the size of the pixel for a backside configuration does not improve MTF performance linearly. Unlike a front side illuminated PMOS pixel there is no vertical overflow drain (reference 8 in FIG. 1). Therefore, photocarriers 233 generated in the deep n-well region 221 can diffuse into adjacent pixels. Near room temperature, photocarriers can diffuse against electric fields of less than 1000 V/cm in magnitude with significant probability. The line defined by electric fields of 1000 V/cm in magnitude is defined as the depletion edge boundary 211, and roughly defines the collection region of a given photodiode 91, 92, 93. Low electric field regions exist both between photodiodes, and between the backside Si/SiO2 interface 250 and the depletion edge boundary 211.
This lateral diffusion degrades the electrical portion of the MTF. The lateral mixing increases with decreasing pixel size, increasing the probability that these photo-induced charge carriers 233 in the low electric field region 215 are collected by the charge collection region 211 of an adjacent pixel. More importantly, for color parts, this can produce color mixing between pixels, and thus degrade image quality.
There is a separate problem with the backside configuration illustrated in FIG. 4. The n-well contact 37 does not make continuous electrical connection to the deep n-well 221. FIG. 5 shows a method for contacting the deep n-well 321 with additional n-type implants 340, 341, 342. However, deeper implants (340 is shallower than 341 which is shallower than 342) have greater lateral straggle. This pinches off the depletion region of the photodiode 311, resulting in a shallower collection depth.
Thus, a need exists for an improved image sensor structure.